Circuit for generating a clock data recovery phase locked indicator and method thereof

Abstract

A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.