The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2014

Filed:

May. 18, 2012
Applicants:

Hyun-seung Yoo, Gyeonggi-do, KR;

Sung-joo Hong, Gyeonggi-do, KR;

Seiichi Aritome, Gyeonggi-do, KR;

Seok-kiu Lee, Gyeonggi-do, KR;

Sung-kye Park, Gyeonggi-do, KR;

Gyu-seog Cho, Gyeonggi-do, KR;

Eun-seok Choi, Gyeonggi-do, KR;

Han-soo Joo, Gyeonggi-do, KR;

Inventors:

Hyun-Seung Yoo, Gyeonggi-do, KR;

Sung-Joo Hong, Gyeonggi-do, KR;

Seiichi Aritome, Gyeonggi-do, KR;

Seok-Kiu Lee, Gyeonggi-do, KR;

Sung-Kye Park, Gyeonggi-do, KR;

Gyu-Seog Cho, Gyeonggi-do, KR;

Eun-Seok Choi, Gyeonggi-do, KR;

Han-Soo Joo, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.


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