The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2014
Filed:
Oct. 19, 2012
Xilinx, Inc., San Jose, CA (US);
Jitu Jain, Los Gatos, CA (US);
Vinay Verma, Fremont, CA (US);
Taneem Ahmed, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Sanjeev Kwatra, Cupertino, CA (US);
Christopher H. Kingsley, Longmont, CO (US);
Jason H. Anderson, Toronto, CA;
Satyaki Das, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.