The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2014

Filed:

Aug. 15, 2012
Applicants:

Rahul Agarwal, Waterford, NY (US);

Ramakanth Alapati, Rexford, NY (US);

Jon Greenwood, Saratoga Springs, NY (US);

Inventors:

Rahul Agarwal, Waterford, NY (US);

Ramakanth Alapati, Rexford, NY (US);

Jon Greenwood, Saratoga Springs, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
Abstract

One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.


Find Patent Forward Citations

Agarwal, Rahul. (2014). Methods of thinning and/or dicing semiconducting substrates having integrated circuit products formed thereon (U.S. Patent No. 8669166). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8669166

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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