The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2014

Filed:

May. 07, 2010
Applicants:

Jaewoong Chung, Bellevue, WA (US);

Debarshi Chatterjee, Mountain View, CA (US);

Inventors:

Jaewoong Chung, Bellevue, WA (US);

Debarshi Chatterjee, Mountain View, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

Some embodiments of a processing system implement a memory-controller-parallelism-aware scheduling technique. In at least one embodiment of the invention, a method of operating a processing system includes scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor according to thread priority information associated with the plurality of threads. The thread priority information is based on a maximum of a plurality of local memory bandwidth usage indicators for each thread of the plurality of threads. Each of the plurality of local memory bandwidth usage indicators for each thread corresponds to a respective memory controller of a plurality of memory controllers.


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Chung, Jaewoong. (2014). Memory-controller-parallelism-aware scheduling for multiple memory controllers (U.S. Patent No. 8667493). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8667493

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