Resistive random memory cell and memory

Abstract

The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory.