The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2014
Filed:
Sep. 24, 2010
Gregory Charles Baldwin, Plano, TX (US);
Thomas J. Aton, Dallas, TX (US);
Kayvan Sadra, Addison, TX (US);
Oluwamuyiwa Oluwagbemiga Olubuyide, Plano, TX (US);
Youn Sung Choi, Plano, TX (US);
Gregory Charles Baldwin, Plano, TX (US);
Thomas J. Aton, Dallas, TX (US);
Kayvan Sadra, Addison, TX (US);
Oluwamuyiwa Oluwagbemiga Olubuyide, Plano, TX (US);
Youn Sung Choi, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.