The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2014

Filed:

Jun. 12, 2012
Applicants:

Shaw-hung Ku, Hsinchu, TW;

Chi-pei LU, Hsinchu, TW;

Chun-lien Su, Hsinchu, TW;

Inventors:

Shaw-Hung Ku, Hsinchu, TW;

Chi-Pei Lu, Hsinchu, TW;

Chun-Lien Su, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.


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