The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2014
Filed:
May. 06, 2013
Texas Instruments Incorporated, Dallas, TX (US);
James Walter Blatchford, Richardson, TX (US);
Yong Seok Choi, Kyunggi-do, KR;
Thomas J. Aton, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width Wover an active area and a neighboring dummy feature having a line width 0.8 Wto 1.3 W. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.