The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2014
Filed:
Jan. 14, 2013
James David Sproch, Monte Sereno, CA (US);
Victor Moroz, Saratoga, CA (US);
Xiaopeng Xu, Cupertino, CA (US);
Aditya Pradeep Karmarkar, Hyderabad, IN;
James David Sproch, Monte Sereno, CA (US);
Victor Moroz, Saratoga, CA (US);
Xiaopeng Xu, Cupertino, CA (US);
Aditya Pradeep Karmarkar, Hyderabad, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.