The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2014

Filed:

Sep. 22, 2011
Applicants:

Michael Piszczek, Laurel, MD (US);

J. Gordon Manning, Ellicott City, MD (US);

Cedric Fernandes, Columbia, MD (US);

Inventors:

Michael Piszczek, Laurel, MD (US);

J. Gordon Manning, Ellicott City, MD (US);

Cedric Fernandes, Columbia, MD (US);

Assignee:

DataDirect Networks, Inc., Chatsworth, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A latency reduction method for read operations of an array of N solid-state storage devices having n solid-state storage devices for data storage and p solid-state storage devices for storing parity data is provided. Utilizing the parity generation engine fault tolerance for a loss of valid data from at least two of the N solid-state storage devices, the integrity of the data is determined when N−1 of the solid-state storage devices have completed executing a read command. If the data is determined to be valid, the missing data of the Nsolid-state storage device is reconstructed and the data transmitted to the requesting processor. By that arrangement the time necessary for the Nsolid-state storage device to complete execution of the read command is saved, thereby improving the performance of the solid-state memory system.

Published as:

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