The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2014
Filed:
Jul. 21, 2005
Michael Bauer, Nittendorf, DE;
Ulrich Bachmaier, Ruderting, DE;
Robert-christian Hagen, Sarching, DE;
Jens Pohl, Bernhardswald, DE;
Rainer Steiner, Regengsburg, DE;
Hermann Vllsmeler, Karlsfeld, DE;
Holger Woerner, Regengsburg, DE;
Bernhard Zuhr, Regengsburg, DE;
Michael Bauer, Nittendorf, DE;
Ulrich Bachmaier, Ruderting, DE;
Robert-Christian Hagen, Sarching, DE;
Jens Pohl, Bernhardswald, DE;
Rainer Steiner, Regengsburg, DE;
Hermann Vllsmeler, Karlsfeld, DE;
Holger Woerner, Regengsburg, DE;
Bernhard Zuhr, Regengsburg, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate, which is electrically connected by way of the wiring substrate on the one hand to external contacts on the underside of the wiring substrate and on the other hand to contact terminal areas in the edge regions of the wiring substrate. The intermediate wiring board has angled-away external flat conductors, which are electrically connected in the contact terminal areas of the wiring board. Furthermore, on the upper side of the intermediate wiring board, arranged on the free ends of the internal flat conductors are external contact terminal areas, which correspond in size and arrangement to external contacts of a semiconductor device to be stacked.