The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Jun. 25, 2012
Anshuman Nayak, San Jose, CA (US);
Samantak Chakrabarti, Kolkata, IN;
Brijesh Agrawal, Greater Noida, IN;
Nitin Bhardwaj, Delhi, IN;
Anshuman Nayak, San Jose, CA (US);
Samantak Chakrabarti, Kolkata, IN;
Brijesh Agrawal, Greater Noida, IN;
Nitin Bhardwaj, Delhi, IN;
Atrenta, Inc., San Jose, CA (US);
Abstract
A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.