The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2014

Filed:

Feb. 23, 2012
Applicants:

Igor Arsovski, Williston, VT (US);

George M. Braceras, Essex Juncton, VT (US);

Harold Pilo, Underhill, VT (US);

Inventors:

Igor Arsovski, Williston, VT (US);

George M. Braceras, Essex Juncton, VT (US);

Harold Pilo, Underhill, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.


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