The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
May. 02, 2012
Luke D. Lacroix, Williston, VT (US);
Mark Lamorey, South Burlington, VT (US);
Janak G. Patel, South Burlington, VT (US);
Peter Slota, Jr., Vestal, NY (US);
David B. Stone, Jericho, VT (US);
Luke D. LaCroix, Williston, VT (US);
Mark Lamorey, South Burlington, VT (US);
Janak G. Patel, South Burlington, VT (US);
Peter Slota, Jr., Vestal, NY (US);
David B. Stone, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.