The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2014

Filed:

Jun. 09, 2011
Applicants:

Yoshitaka Sasaki, Santa Clara, CA (US);

Hiroyuki Ito, Milpitas, CA (US);

Hiroshi Ikejima, Hong Kong, CN;

Atsushi Iijima, Hong Kong, CN;

Inventors:

Yoshitaka Sasaki, Santa Clara, CA (US);

Hiroyuki Ito, Milpitas, CA (US);

Hiroshi Ikejima, Hong Kong, CN;

Atsushi Iijima, Hong Kong, CN;

Assignees:

Headway Technologies, Inc., Milpitas, CA (US);

SAE Magnetics (H.K.) Ltd., Hong Kong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.


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