The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Jun. 14, 2012
Alwin James Tsao, Garland, TX (US);
Purushothaman Srinivasan, Allen, TX (US);
Alwin James Tsao, Garland, TX (US);
Purushothaman Srinivasan, Allen, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.