The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2014
Filed:
Jun. 30, 2011
Arturo Salz, Menlo Park, CA (US);
Guillermo R. Maturana, Berkeley, CA (US);
In-ho Moon, Portland, OR (US);
Lisa R. Mcilwain, Oregon City, OR (US);
Arturo Salz, Menlo Park, CA (US);
Guillermo R. Maturana, Berkeley, CA (US);
In-Ho Moon, Portland, OR (US);
Lisa R. McIlwain, Oregon City, OR (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification.