The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2014

Filed:

Jan. 31, 2012
Applicants:

Rinji Sugino, San Jose, CA (US);

Yider Wu, Taipei County, TW;

Minh Van Ngo, Fremont, CA (US);

Jeffrey Sinclair Glick, Cupertino, CA (US);

Kuo Tung Chang, Saratoga, CA (US);

Inventors:

Rinji Sugino, San Jose, CA (US);

Yider Wu, Taipei County, TW;

Minh Van Ngo, Fremont, CA (US);

Jeffrey Sinclair Glick, Cupertino, CA (US);

Kuo Tung Chang, Saratoga, CA (US);

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.


Find Patent Forward Citations

Sugino, Rinji. (2014). Method for forming a semiconductor layer with improved gap filling properties (U.S. Patent No. 8647969). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8647969

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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