The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

Nov. 26, 2012
Applicant:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Inventors:

Ban P. Wong, Milpitas, CA (US);

Brad Sharpe-Geisler, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A ball-grid-array (BGA) package is disclosed that includes traces within a BGA substrate. At least one of the traces is configured to match a low-impedance load presented by a BGA substrate pad and associated circuitry on a flip-chip die to an impedance of a circuit board trace. Each configured trace includes a relatively narrow section coupling to a tapered section that widens from the relatively narrow section to join a relatively wider trace section.


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Wong, Ban. (2014). Integrated circuit package with input capacitance compensation (U.S. Patent No. 8643168). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8643168

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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