The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
Jan. 18, 2010
Ryuta Tsuchiya, Tokyo, JP;
Nobuyuki Sugii, Tokyo, JP;
Yusuke Morita, Akishima, JP;
Hiroyuki Yoshimoto, Kawasaki, JP;
Takashi Ishigaki, Hino, JP;
Shinichiro Kimura, Kunitachi, JP;
Ryuta Tsuchiya, Tokyo, JP;
Nobuyuki Sugii, Tokyo, JP;
Yusuke Morita, Akishima, JP;
Hiroyuki Yoshimoto, Kawasaki, JP;
Takashi Ishigaki, Hino, JP;
Shinichiro Kimura, Kunitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.