The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Jan. 27, 2012
Gradus (Geert) Janssen, Putnam Valley, NY (US);
Luis Lastras-montano, Cortlandt Manor, NY (US);
Alexey Y. Lvov, Congers, NY (US);
Viresh Paruthi, Austin, TX (US);
Robert Shadowen, Austin, TX (US);
Barry M. Trager, Yorktown Heights, NY (US);
Shmuel Winograd, Scarsdale, NY (US);
Ali El-zein, Austin, TX (US);
Gradus (Geert) Janssen, Putnam Valley, NY (US);
Luis Lastras-Montano, Cortlandt Manor, NY (US);
Alexey Y. Lvov, Congers, NY (US);
Viresh Paruthi, Austin, TX (US);
Robert Shadowen, Austin, TX (US);
Barry M. Trager, Yorktown Heights, NY (US);
Shmuel Winograd, Scarsdale, NY (US);
Ali El-Zein, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.