The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Mar. 25, 2003
Gulbin Ayse Ezer, Los Gatos, CA (US);
Pavlos Konas, Mountain View, CA (US);
John Barrett Andrews, Sunnyvale, CA (US);
Stephen Wei Chou, San Jose, CA (US);
Eileen Margaret Peters Long, San Jose, CA (US);
Marc Alan Evans, San Jose, CA (US);
Gulbin Ayse Ezer, Los Gatos, CA (US);
Pavlos Konas, Mountain View, CA (US);
John Barrett Andrews, Sunnyvale, CA (US);
Stephen Wei Chou, San Jose, CA (US);
Eileen Margaret Peters Long, San Jose, CA (US);
Marc Alan Evans, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An automated system-on-chip (SOC) hardware and software cogeneration design flow allows an SOC designer, using a single source description for any platform-independent combination of reused or new IP blocks, to produce a configured hardware description language (HDL) description of the circuitry necessary to implement the SOC, while at the same time producing the development tools (e.g., compilers, assemblers, debuggers, simulator, software support libraries, reset sequences, etc.) used to generate the SOC software and the diagnostics environment used to verify the SOC.