The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Jun. 03, 2013
Teak-hoon Lee, Hwaseong-si, KR;
Won-keun Kim, Hwaseong-si, KR;
Dong-hyeon Jang, Yongin-si, KR;
Ho-geon Song, Suwon-si, KR;
Sung-jun Im, Yongin-si, KR;
Teak-hoon Lee, Hwaseong-si, KR;
Won-keun Kim, Hwaseong-si, KR;
Dong-hyeon Jang, Yongin-si, KR;
Ho-geon Song, Suwon-si, KR;
Sung-jun Im, Yongin-si, KR;
Abstract
A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.