The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2014

Filed:

Oct. 17, 2011
Applicants:

Effendi Leobandung, Wappinger Falls, NY (US);

Dae-gyu Park, Poughquaq, NY (US);

Shom S. Ponoth, Clifton Park, NY (US);

Zhibin Ren, Hopewell Junction, NY (US);

Ghavam G. Shahidi, Pound Ridge, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Inventors:

Effendi Leobandung, Wappinger Falls, NY (US);

Dae-Gyu Park, Poughquaq, NY (US);

Shom S. Ponoth, Clifton Park, NY (US);

Zhibin Ren, Hopewell Junction, NY (US);

Ghavam G. Shahidi, Pound Ridge, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/336 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76251 (2013.01); H01L 29/78603 (2013.01);
Abstract

Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.


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