The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8634452 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 21, 2014

Filed:

Jun. 07, 2012
Applicants:

Jared L. Zerbe, Woodside, CA (US);

Bruno W. Garlepp, Austin, TX (US);

Pak S. Chau, San Jose, CA (US);

Kevin S. Donnelly, Los Altos, CA (US);

Mark A. Horowitz, Menlo Park, CA (US);

Stefanos Sidiropoulos, Palo Alto, CA (US);

Billy W. Garrett, Jr., Mountain View, CA (US);

Carl W. Werner, San Jose, CA (US);

Inventors:

Jared L. Zerbe, Woodside, CA (US);

Bruno W. Garlepp, Austin, TX (US);

Pak S. Chau, San Jose, CA (US);

Kevin S. Donnelly, Los Altos, CA (US);

Mark A. Horowitz, Menlo Park, CA (US);

Stefanos Sidiropoulos, Palo Alto, CA (US);

Billy W. Garrett, Jr., Mountain View, CA (US);

Carl W. Werner, San Jose, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.


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