The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2014
Filed:
Oct. 21, 2010
Dong-hee Yu, Hwaseong-si, KR;
Bong-seok Suh, Hwaseong-si, KR;
Yoon-hae Kim, Yongin-si, KR;
O Sung Kwon, Wappingers Falls, NY (US);
Oh-jung Kwon, Hopewell Junction, NY (US);
Dong-Hee Yu, Hwaseong-si, KR;
Bong-Seok Suh, Hwaseong-si, KR;
Yoon-Hae Kim, Yongin-si, KR;
O Sung Kwon, Wappingers Falls, NY (US);
Oh-Jung Kwon, Hopewell Junction, NY (US);
Samsung Electronics Co., Ltd., , KR;
Infineon Technologies AG, Neubiberg, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.