The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
May. 01, 2012
Applicants:
Subramani Kengeri, San Jose, CA (US);
Chung-cheng Chou, Hsinchu, TW;
Bharath Upputuri, Santa Clara, CA (US);
Hank Cheng, Taichung, TW;
Ming-zhang Kuo, Tainan County, TW;
Pey-huey Chen, Baoshan Township, TW;
Inventors:
Subramani Kengeri, San Jose, CA (US);
Chung-Cheng Chou, Hsinchu, TW;
Bharath Upputuri, Santa Clara, CA (US);
Hank Cheng, Taichung, TW;
Ming-Zhang Kuo, Tainan County, TW;
Pey-Huey Chen, Baoshan Township, TW;
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.