The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2014
Filed:
Feb. 23, 2012
Ko-chi Chen, Taoyuan County, TW;
Ping-chia Shih, Tainan, TW;
Chih-ming Wang, Tainan, TW;
Chi-cheng Huang, Kaohsiung, TW;
Hsiang-chen Lee, Kaohsiung, TW;
Ko-Chi Chen, Taoyuan County, TW;
Ping-Chia Shih, Tainan, TW;
Chih-Ming Wang, Tainan, TW;
Chi-Cheng Huang, Kaohsiung, TW;
Hsiang-Chen Lee, Kaohsiung, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.