The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Nov. 13, 2009
Hiroyuki Kutsukake, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Mitsuhiro Noguchi, Yokohama, JP;
Kikuko Sugimae, Yokohama, JP;
Masato Endo, Yokohama, JP;
Takuya Futatsuyama, Yokohama, JP;
Koji Kato, Yokohama, JP;
Kanae Uchida, Yokohama, JP;
Hiroyuki Kutsukake, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Mitsuhiro Noguchi, Yokohama, JP;
Kikuko Sugimae, Yokohama, JP;
Masato Endo, Yokohama, JP;
Takuya Futatsuyama, Yokohama, JP;
Koji Kato, Yokohama, JP;
Kanae Uchida, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.