The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8621426 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 31, 2013

Filed:

Apr. 22, 2010
Applicant:

Satwant Kaur, San Jose, CA (US);

Inventor:

Satwant Kaur, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods of conducting interoperability assessments provide for generating a feature interoperability matrix based on feature data and interoperability data, wherein the feature data defines a plurality of features of a product and the interoperability data indicates levels of interoperability of the plurality of features. A validation set can be generated based on the feature interoperability matrix, wherein the validation set includes a plurality of feature combinations. A subfeature interoperability matrix can be used to convert the validation set into a test plan for the product, wherein the test plan minimizes test configurations for the product.


Find Patent Forward Citations

Kaur, Satwant. (2013). Automated top down process to minimize test configurations for multi-feature products (U.S. Patent No. 8621426). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8621426

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…