The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2013
Filed:
Jul. 12, 2012
Woon-seong Kwon, Cupertino, CA (US);
Suresh Ramalingam, Fremont, CA (US);
Woon-Seong Kwon, Cupertino, CA (US);
Suresh Ramalingam, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile