The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2013
Filed:
Nov. 05, 2009
Brian Matthew Henderson, San Diego, CA (US);
Shiqun Gu, San Diego, CA (US);
Homyar C. Mogul, San Diego, CA (US);
Mark M. Nakamoto, San Diego, CA (US);
Arvind Chandrasekaran, San Diego, CA (US);
Brian Matthew Henderson, San Diego, CA (US);
Shiqun Gu, San Diego, CA (US);
Homyar C. Mogul, San Diego, CA (US);
Mark M. Nakamoto, San Diego, CA (US);
Arvind Chandrasekaran, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.