The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

Aug. 26, 2010
Applicants:

Shao-yen Ku, Jhubei, TW;

Chi-ming Yang, Hsin-Chu, TW;

Ming-tsao Chiang, Jhubei, TW;

Yu-fen Tzeng, Hsinchu, TW;

Chin-hsiang Lin, Hsinchu, TW;

Inventors:

Shao-Yen Ku, Jhubei, TW;

Chi-Ming Yang, Hsin-Chu, TW;

Ming-Tsao Chiang, Jhubei, TW;

Yu-Fen Tzeng, Hsinchu, TW;

Chin-Hsiang Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67011 (2013.01); H01L 21/67155 (2013.01); H01L 21/677 (2013.01); H01L 21/67703 (2013.01); Y10S 414/135 (2013.01); Y10S 414/139 (2013.01);
Abstract

The present disclosure provides a system and method for processing a semiconductor substrate wherein a substrate is received at a load lock interface. The substrate is transferred from the load lock interface to a process module using a first module configured for unprocessed substrates. A manufacturing process is performed on the substrate within the process module. Thereafter, the substrate is transferred from the process module to the load lock interface using a second module configured for processed substrates.


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