The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2013

Filed:

Mar. 06, 2007
Applicants:

Richard C Dokken, San Ramon, CA (US);

Gerald S. Chan, Saratoga, CA (US);

John C Potter, Austin, TX (US);

Alfred L Crouch, Cedar Park, TX (US);

Inventors:

Richard C Dokken, San Ramon, CA (US);

Gerald S. Chan, Saratoga, CA (US);

John C Potter, Austin, TX (US);

Alfred L Crouch, Cedar Park, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.


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