The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Apr. 01, 2011
Applicants:

Darrell S. Mcginnis, Cornelius, OR (US);

C. Scott Huddleston, Beaverton, OR (US);

Rajat Agarwal, Beaverton, OR (US);

Meenakshisundaram R. Chinthamani, Hillsboro, OR (US);

Inventors:

Darrell S. McGinnis, Cornelius, OR (US);

C. Scott Huddleston, Beaverton, OR (US);

Rajat Agarwal, Beaverton, OR (US);

Meenakshisundaram R. Chinthamani, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.


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