The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Jul. 22, 2011
Applicants:

Clement Hsingjen Wann, Carmel, NY (US);

Chih-hsin Ko, Fongshan, TW;

Yao-tsung Huang, Kaohsiung, TW;

Cheng-ying Huang, Kaohsiung, TW;

Inventors:

Clement Hsingjen Wann, Carmel, NY (US);

Chih-Hsin Ko, Fongshan, TW;

Yao-Tsung Huang, Kaohsiung, TW;

Cheng-Ying Huang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.


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