The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2013
Filed:
Mar. 09, 2012
Mohamed Shaker Sarwary, San Diego, CA (US);
Maher Mneimneh, San Jose, CA (US);
Paras Mal Jain, Greater Noida, IN;
Deepak Ahuja, Delhi, IN;
Mohammad Homayoun Movahed-ezazi, Saratoga, CA (US);
Mohamed Shaker Sarwary, San Diego, CA (US);
Maher Mneimneh, San Jose, CA (US);
Paras Mal Jain, Greater Noida, IN;
Deepak Ahuja, Delhi, IN;
Mohammad Homayoun Movahed-Ezazi, Saratoga, CA (US);
Atrenta, Inc., San Jose, CA (US);
Abstract
Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.