The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Apr. 21, 2011
Applicants:

Chungte Hsuan, Hsinchu, TW;

Chao-lung Lo, Jhubei, TW;

Tien-chu Yang, Hsinchu, TW;

Tahone Yang, Hsinchu, TW;

Kuang-chao Chen, Hsinchu County, TW;

Chien Hung Chen, Fongshan, TW;

Inventors:

Chungte Hsuan, Hsinchu, TW;

Chao-Lung Lo, Jhubei, TW;

Tien-Chu Yang, Hsinchu, TW;

Tahone Yang, Hsinchu, TW;

Kuang-Chao Chen, Hsinchu County, TW;

Chien Hung Chen, Fongshan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.


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