The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Sep. 23, 2011
Applicants:

Abhijeet Ashok Chachad, Plano, TX (US);

Roger Kyle Castille, Houston, TX (US);

Joseph Raymond Michael Zbiciak, Arlington, TX (US);

Dheera Balasubramanian, Richardson, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Roger Kyle Castille, Houston, TX (US);

Joseph Raymond Michael Zbiciak, Arlington, TX (US);

Dheera Balasubramanian, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/04 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.


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