The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2013
Filed:
Sep. 24, 2011
Satoshi Yamada, Kanagawa, JP;
Takashi Karashima, Kanagawa, JP;
Kenya Hironaga, Kanagawa, JP;
Masatoshi Yasunaga, Kanagawa, JP;
Yuji Fujimoto, Kanagawa, JP;
Satoshi Yamada, Kanagawa, JP;
Takashi Karashima, Kanagawa, JP;
Kenya Hironaga, Kanagawa, JP;
Masatoshi Yasunaga, Kanagawa, JP;
Yuji Fujimoto, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (−). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.