The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Dec. 19, 2012
Applicant:

Elpida Memory, Inc., Tokyo, JP;

Inventors:

Satoshi Itaya, Tokyo, JP;

Kayoko Shibata, Tokyo, JP;

Shoji Azuma, Tokyo, JP;

Akira Ide, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.


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