The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Dec. 20, 2012
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Nanhai Li, Pleasanton, CA (US);

William Thie, Fremont, CA (US);

Novy Tjokro, San Ramon, CA (US);

Yaxin Wang, Fremont, CA (US);

Artur Kolics, Dublin, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming semiconductor devices on a substrate under a porous low-k dielectric layer, wherein features are formed in the porous low-k dielectric layer and wherein a barrier layer is formed over the porous low-k dielectric layer is provided. Contacts are formed in the features. The barrier layer is planarized. A cap layer is formed over the contacts, wherein the forming the cap layer provides metal and organic contaminants in the porous low-k dielectric layer. The metal contaminants are removed from the porous low-k dielectric layer with a first wet process. The organic components are removed from the porous low-k dielectric layer with a second wet process.


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