The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Dec. 22, 2008
Method and system for schematic-visualization driven topologically-equivalent layout design in rfsip
Applicants:
Alok Tripathi, Noida, IN;
Abha Jain, Greater Noida, IN;
Parag Choudhary, Noida, IN;
Utpal Bhattacharya, Noida, IN;
Inventors:
Alok Tripathi, Noida, IN;
Abha Jain, Greater Noida, IN;
Parag Choudhary, Noida, IN;
Utpal Bhattacharya, Noida, IN;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.