The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Jun. 21, 2011
Dipankar Bhattacharya, Macungie, PA (US);
Ashish V. Shukla, Allentown, PA (US);
John Christopher Kriz, Palmerton, PA (US);
Makeshwar Kothandaraman, Bangalore, IN;
Pankaj Kumar, Bangalore, IN;
Pramod Parameswaran, Bangalore, IN;
Dipankar Bhattacharya, Macungie, PA (US);
Ashish V. Shukla, Allentown, PA (US);
John Christopher Kriz, Palmerton, PA (US);
Makeshwar Kothandaraman, Bangalore, IN;
Pankaj Kumar, Bangalore, IN;
Pramod Parameswaran, Bangalore, IN;
LSI Corporation, San Jose, CA (US);
Abstract
A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.