Self aligned mos structure with polysilicon contact

Abstract

A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon. The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region. The method selectively removes the capping layer overlying the gate structure. The method then forms a silicide layer overlying the gate structure and surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon.