The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Jul. 24, 2013
Applicant:
Lajos Burgyan, Mountain View, CA (US);
Inventor:
Lajos Burgyan, Mountain View, CA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Three dimensional Panel-Level Packaging (3D-PLP) fabrication techniques for mass-production of small, simple three dimensional electronic component packages or units such as a DC-DC Converters are described where each package or unit consists of at least an active semiconductor die and a passive, two-terminal electrical circuit element (capacitor inductor and/or resistor).
Burgyan, Lajos. (2013). Panel-level package fabrication of 3d active semiconductor and passive circuit components (U.S. Patent No. 8597979). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8597979
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile