Architectural physical synthesis

Abstract

The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources. In addition, incremental area removal method can be utilized to address resource utilization problem through a quality metric based on force directed placement transforms, such as a resource demand topological mapping.