The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8594988 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 26, 2013

Filed:

Jun. 21, 2007
Applicants:

Athanasius W. Spyrou, Sunnyvale, CA (US);

Arnold Ginetti, Antibes, FR;

Inventors:

Athanasius W. Spyrou, Sunnyvale, CA (US);

Arnold Ginetti, Antibes, FR;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 7/60 (2006.01); G06F 17/10 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.


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Spyrou, Athanasius. (2013). Method and apparatus for circuit simulation using parallel computing (U.S. Patent No. 8594988). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8594988

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