The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Jul. 13, 2010
Pius NG, Hillsboro, OR (US);
Satish Padmanabhan, Sunnyvale, CA (US);
Anand Pandurangan, Bangalore, IN;
Ananth Durbha, San Jose, CA (US);
Suresh Kadiyala, Cupertino, CA (US);
Gary Oblock, Santa Clara, CA (US);
Pius Ng, Hillsboro, OR (US);
Satish Padmanabhan, Sunnyvale, CA (US);
Anand Pandurangan, Bangalore, IN;
Ananth Durbha, San Jose, CA (US);
Suresh Kadiyala, Cupertino, CA (US);
Gary Oblock, Santa Clara, CA (US);
Algotochip Corp., Sunnyvale, CA (US);
Abstract
Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.